1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, and more specifically, to a method for fabricating a MOS transistor.
2. Description of the Related Art
Common use of highly integrated mobile devices results in accelerating the development of a CMOS transistor capable of working at a low power. The method for fabricating such a CMOS transistor may benefit from a process for decreasing leakage current. However, such a process may deteriorate the performance of a CMOS device. To solve this problem, a variety of methods for fabricating a CMOS transistor having both low leakage current and high performance have been developed. Such methods include a Ge-implantation or a strained Si structure, formed by use of a Ge—Si epitaxial film.
FIGS. 1a to 1f show a conventional method for fabricating a CMOS transistor. As shown in the figures, a method for manufacturing an n-type MOS transistor is as follows.
Firstly, SiO2 is deposited as a sacrificial layer for an ion-implantation to form a retro-grade well on a silicon substrate of a semiconductor, which is not shown in the figure. After implanting the ions, the silicon oxide layer is deleted to form a well, a field stop and a channel region.
As shown in FIG. 1a, SiO2 may be deposited as a gate insulating layer 12 on a semiconductor silicon substrate 10 by CVD, then doped Polysilicon is deposited as a conductive layer of a gate electrode 14 by LPCVD. After patterning the conductive layer by photolithography and a dry-etching process such as RIE, etc. using a gate mask, a gate electrode 14, a gate insulating layer 12 under the gate electrode 14 is formed.
After sidewall oxidation of the gate electrode 14, a LDD region 15 is formed on the surface of the silicon substrate exposed by the gate electrode 14 by implanting an n-type dopant, for example P or As in a low concentration.
As shown in FIG. 1b, after depositing a first insulating layer 16 for example, TEOS on an entire surface of the resulting product by LP-CVD, a second layer 18 for example, Si3N4 is deposited on the first insulating layer 16.
Next, as shown in FIG. 1c, the second insulating layer and the first insulating layer are etched by a dry-etching process such as self-aligned RIE to form spacers 16a and 18a on sidewalls of the gate electrode 14.
Subsequently, as shown FIG. 1d, an n-type dopant for example P or As is implanted in a high concentration using the gate electrode 14 and spacers 16a and 18a as masks to form a source/drain region 20 in the silicon substrate 10 exposed by spacers 16a and 18a. 
Next, as shown in FIG. 1e, Si3N4 as an etch stopping layer 22 is deposited on an entire surface of the result product by LP-CVD, to obtain a low leakage current property instead of applying a silicide process.
Next, as shown in FIG. 1f, after depositing BPSG as an ILD (Interlevel Dielectric) layer on the top of the etch stopping layer 22 by CVD, TEOS/SiH4 as a capping layer, which is not shown in figures, is deposited on the BPSG layer. A contact hole is formed in the capping layer, the ILD layer and the etch-stopping layer 22 to open the source/drain region 20 or the gate electrode 14. After filling the contact hole with a conductive layer such as doped polysilicon or tungsten, the surface of the conductive layer is planarized by CMP to make a contact electrode 24.
In an n-type MOS transistor formed by a conventional fabrication method, high stress in the channel (b) between a LDD region 15 and a source/drain region 20 by punch-through may reduce carrier mobility. As a result, the performance of a CMOS device may decrease.